1. Field of the Invention
The present invention relates to a joining method for joining two joining target members, e.g., a lead frame and a chip of a semiconductor device, with solder or the like, and to a semiconductor device manufacturing method using the same.
2. Description of the Background Art
Two joining target members, e.g., a lead frame and a semiconductor chip (which hereinafter may simply be referred to as the “chip”) of a semiconductor device are joined to each other with a joining material such as solder. According to joining methods of conventional techniques, a heat spreader on which a lead frame and a chip are mounted is tentatively assembled before being put into an oven, and molten solder is supplied from a solder supply source in the oven. By solidifying the supplied molten solder, the lead frame and the chip are joined to each other (for example, see Japanese Patent Application Laid-Open No. 2008-182074).
According to the joining methods of the conventional techniques such as disclosed in Japanese Patent Application Laid-Open No. 2008-182074, since the solder supply source supplying the solder is provided one in number, the solder cannot be supplied to a plurality of portions at once. In the case where the solder is supplied to a plurality of portions, the molten solder must be supplied to those portions one by one in order, and hence it takes time.
Further, since the heat must be retained while the molten solder is supplied, the base material of the chip may be influenced by the molten solder at the portions where the molten solder has already been supplied. For the purpose of suppressing the influence, the heating time and the processing speed in the joining processing are restricted. Therefore, the time from when the supply of solder is started in the oven until when the supply ends is restricted. This is referred to as the supply time restriction. The supply time restriction poses a problem that the number of chips mounted on a semiconductor device cannot be increased.